Live Webcast 15th Annual Charm++ Workshop

Interprocessor communication time is one of the major performance bottlenecks in parallel applications . Consequently performance prediction of parallel applications requires an accurate prediction of communication time. Accurate prediction of communication time involves detailed modeling of entities in the interconnection network. Such a detailed modeling also helps in designing message passing layers for current and future systems . This masters thesis describes a detailed parallel discrete event based simulator for the interconnection networks used in high performance computing machines. We have simulated an example each in the direct and indirect class of interconnection networks . Fat Tree network, which is employed in most of the current top 10 clusters will be the candidate for simulation of an indirect network. More specifically QSNET will be used for fat tree simulation. IBM Bluegene/L which is a next generation supercomputer will be used as an example for simulating a direct network.